CODEWITHSUNDEEP
vhdl
ted
ted

Reputation: 4975

Define "enum"-type depending on generics

I am writing a statemachine, which has a generic parameter, and some states existence depends on this. Since I have my states defined in something like an enum (don't know the vhdl term for it), I wonder if I can define this enum depending on the generic somewhat like so:

generic(x: bool);  -- in the entity
....

architecture ...
    if x then generate
        type states_t is (State1, State2, State3ifX)
    else
        type states_t is (State1, State2)
    end generate;
    variable state : states_t;
begin
   case state is
       ....
       if x then generate
           when State3ifX =>
                ...
       end if;
   end case
end architecture;

Do I have to carry the dead weight (logic for state3, danger to drop into it (does not matter in my case since I do not expect radiation), additional bit since ceil(ld(3))=2 > ld(2)=1), or is there a possibility to strip unnecessary state(s)?

(In my case there are several states that could be stripped, however seperate architectures are not worth while the effort)

Upvotes: 1

Views: 794

Answers (3)

Tomasz Janicki
Tomasz Janicki

Reputation: 99

I know its an old tread but still a hit on google so Im adding how Im doing it

label: if x generate

declarations <- put types, signals & attribures here !!!!

begin

ur code

end generate label;

You might want to consider second architecture or even simpler just a different entity - just another vhd file with slightly different name (like _x1, then _x2)

I find "genercis system" not really practical in more advanced cases (to much bloat-code to write), and then u might use different synthezisers so two archoitecture with one entity might not work, generate with decalrations inside might not work.... I would create different vhd for that - it will work in all the cases)

Cheers

Upvotes: -1

Martin Thompson
Martin Thompson

Reputation: 16812

I can't think of a way to achieve what you need.

On the upside, your concern about having to "carry the dead weight (logic for state3, danger to drop into it)" is not something you need to worry about - the synthesizer will optimise the logic away, so the state register will only be as big as it needs to be for the states you can actually reach.

Upvotes: 1

baldyHDL
baldyHDL

Reputation: 1387

you can define the "states"-type in a process that is optionally generated using a generic. see a reference example below:

entity blabla is
   generic(sel: std_logic := '0');
port(
...

architecture Behavioral of blabla is
begin

q1: if sel='0' generate
p: process(clk)
    type t_state is (s1, s2, s3);
    variable state: t_state;
begin
    if rising_edge(clk) then
       ...
    end if;
end process;
end generate;

q2: if sel='1' generate
p: process(clk)
    type t_state is (s1, s2);
    variable state: t_state;
begin
    if rising_edge(clk) then
        ...
    end if;
end process;
end generate;

Upvotes: 2

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