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verilogclockxilinx
Bharath
Bharath

Reputation: 1

Maximum Clock Determination in Xilinx ISE 14.4

I have a piece of code implemented in Verilog which calculates centroid of an image.
I have simulated the code using Xilinx ISIM simulator in Post place and route mode and it works well, now I want to determine the maximum clock speed at which the code can run.
The Design summary in its Clock report indicates that Max Delay is 0.057 nsec does that mean I can have a clock speed less than 1/0.057 nsec or is there any other indication of maximum possible clock speed.

Upvotes: 0

Views: 2330

Answers (1)

alex_milhouse
alex_milhouse

Reputation: 901

there are several factors in determining this, and you may need more information that just max delay (for instance jitter, hold times, setup times, etc). The clock speed will certainly not be less then 1/.057ns which is equal to 17GHz. Also, what is your target for this design? because if it is for an FPGA then you will not be able to go past the specs for your current chip.

If you go to your xst.log file (that is if you had vivado/ISE print out a report then) and you go to the bottom of that file it will give you a timing summary. one of those lines will say:

Minimum period: x ns (Maximum Frequency: X MHz) this will tell you how fast you can run.

Upvotes: 1

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