CODEWITHSUNDEEP
arraysvhdl
Amitai weil
Amitai weil

Reputation: 1

signal x is array (1 to n) of type - VHDL

I'm writing a code in VHDL language and there's something I want to implement: An array of FSM situations.

so I wrote as follows: type C_state_type is (IDLE_C, X_chk_C, O_chk_C, tmp_draw_C);
signal cur_st_C, nxt_st_C is array (1 to n) of C_state_type;

any idea if this can be implemented somehow? If so, what should I change? because modelsim doesn't agree to this.

Thanks, Amitai

Upvotes: 0

Views: 104

Answers (1)

baldyHDL
baldyHDL

Reputation: 1387

define the array as TYPE too. then define the signals as your array. e.g.

type C_state_type is (IDLE_C, X_chk_C, O_chk_C, tmp_draw_C);
type C_state_array is array (1 to n) of C_state_type;
signal cur_st_C, nxt_st_C: C_state_array;

Upvotes: 1

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