Address Value in Assembly

Question

I have the following assembly program :

My question is : Why does the Address Value increases by 3h in every process and sometimes its only increases by 1h like :

0010h 0011h 0012h . . .

Answer 1

Because the machine code in this case ^(a) isn't a fixed number of bytes per instruction, it varies depending on the instruction itself. You can see the bytes making up each instruction in the opcode column.

The instruction at 0010 takes three bytes with the aa meaning load an immediate byte into a register, the 00 meaning register r0, and the 02 giving the immediate byte value to load. This is evident because the same aa opcode is used to load up r1 in the following instruction.

Contrast that with the instruction at 0019 which has the two bytes d4 20. The length of the instruction is what controls the address of the following instruction.

Perhaps expanding it out may help your understanding:

0010  AA  MAIN:  MVI R0, 2
0011  00
0012  02

0013  AA         MVI R1, -1
0014  10
0015  FF

0016
:

An instruction tends to consist of an opcode which controls what is to be done, along with other information giving more fine-grained details (the operands) which may provide such things as immediate data or addressing modes (immediate, memory, indexed, I/O ports, scaled and a whole host of other possibilities). For example, it's evident from your example that aa is the load register immediate opcode that works as follows:

aa x0 yy    ; rx <- yy
|| |  ||
|| |  ++--> immediate byte to load in to register
|| +------> register to receive byte
++--------> fixed opcode aa

Similarly, the add instruction at 001e indicates how to add two registers together:

b2 xy       ; rx <- rx + ry
|| ||
|| |+-----> register to add to rx
|| +------> register to receive sum (rx)
++--------> fixed opcode b2

A final example of the opcode/operands dichotomy is the jump instruction (actually both them, jmp and jnz) - it has a controlling opcode with the next two bytes specifying the absolute address to jump to (in little-endian format).

---

^(a) Certainly there are architectures where instructions are fixed length such as on certain RISC CPUs where the fixed lengths (and fixed positions of fields within the instruction) enabled the instruction decoding to be much simpler (and therefore, hopefully, much faster).

The particular architecture in your question is, however, not one of those.