CODEWITHSUNDEEP
verilog
Doov
Doov

Reputation: 863

Parameterized number of cycle delays in verilog?

I have to delay a few control signals in a pipeline I've designed by the number of stages in the pipeline. This is obviously very straight forward -- just put N flip-flops in between the the input signal and output signal. I'm wondering if there's a way to parameterize N. If I ever change the number of stages in the pipeline I have to go back and add/remove flip-flops, which is sort of annoying. I thought about just writing a script to read a define somewhere and generate the module, but that seems like overkill. Is a genvar loop the right way to go here?

Upvotes: 3

Views: 6329

Answers (2)

IWantAnalogHDL
IWantAnalogHDL

Reputation: 306

You could use a parameterized shift register to do this. Something like: 

module shift
(
  input clk,
  input data_in,
  output data_out
);

parameter DEPTH = 3;
reg [DEPTH-1:0] holding_register;

always @ (posedge clk) begin
  holding_register <= {holding_register[DEPTH-2:0], data_in};
end

assign data_out = holding_register[DEPTH-1];

endmodule

Another alternative would be to use a generate statement to create essentially the same effect.

Upvotes: 8

Victor L
Victor L

Reputation: 10230

Here is how to created the parameterized shift register using a generate block and a DFF module. It even works with DEPTH=0 and DEPTH=1.

module shift
(
  input clk,
  input reset,
  input data_in,
  output data_out
);

parameter DEPTH = 3;
wire [DEPTH:0] connect_wire;

assign data_out = connect_wire[DEPTH];
assign connect_wire[0] = data_in;

genvar i;
generate
   for (i=1; i <= DEPTH; i=i+1) begin
      dff DFF(clk, reset,
        connect_wire[i-1], connect_wire[i]);
   end
endgenerate

endmodule

Complete working code with a test on EDA Playground: http://www.edaplayground.com/s/4/50

Upvotes: 2

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