CODEWITHSUNDEEP
typesinstructionsvm-implementation
user2341104
user2341104

Reputation:

VM - reducing number of instructions for different types?

I am developing an experimental VM, and right now I have a separate instruction for all datatype operations for each and every type, just to be safe. E.g. I have an ADD instruction for 8, 16, 32 and 64 bit signed and unsigned integers, as well as for float, double and long double. That's 11 instructions for one operation. Now it is true that some operations support only certain types, but even so, I end up with a lot of instructions and very little head room.

So I am wondering if some instructions can operate regardless of the underneath type, so I can cut the number and make room for more instructions that I'll be in desperate need of in the future, since I don't want to exceed a byte for the instruction.

Upvotes: 1

Views: 155

Answers (3)

cyon
cyon

Reputation: 9548

The Java VM solves this problem by only supporting certain operations like ADD, SUB for the types long (64) , double(64 fp) and int (32). It then provides a number of conversion instructions to convert from 32 bit types to 16 and 8 bit (signed and unsigned).

Of course, this approach is only advantageous if the number of needed conversion operations is less then the number operations you would end up with if you had a special ADD, SUB, MUL, DIV etc for every type.

If an addition of two 16 bit variables is required you move them to 32 bit registers with a 16_to_32 instruction and perform a 32 bit ADD_32. And then you take the result and convert it to 16 variable bit with an 32_to_16 bit operation which truncates the result to fit a 16 bit variable.

Your x_to_y instructions could then take care of the sign-extensions or zero-extensions required for signed or unsigned conversion.

If you are interested in how the jvm does this have a look at the jvm spec.

Upvotes: 0

Puppy
Puppy

Reputation: 147056

You don't have an awful lot of choice, unless each expression carries it's own type information at run-time.

How real processors do it is to have an opcode, and then a kind of operand code that tells the processor what kind of operand to use. For example, you might say

enum Operator {
    Add,
    Sub,
    And,
    ...
};
enum Operand {
    Memory,
    Immediate,
    Reg1,
    Reg2,
    ...
};
struct Instruction {
    Operator op;
    Operand lhs;
    Operand rhs;
};

Also, some instructions like add and sub don't need to know the difference between signed and unsigned. That's one of the upsides of 2's complement.

Typically, each register is of a fixed width (e.g. 32bit for x86) and then if you want to operate on the lowest eight bits, you mask out the other 24 with an AND operation first. Of course, on x86 you can still use the 8-bit, 16-bit registers to refer to parts of a 32bit register in some cases, I think.

Upvotes: 1

A. H.
A. H.

Reputation: 952

Instead of having ADD , SUB , etc.. for every data type why not have them operate on "registers" and have MOV like instruction for all the datatypes that will zero out/sign extend the rest (if any) of the register.

This is of course assuming you have things like that in your VM. You might want to add more information to your question.

Upvotes: 1

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