CODEWITHSUNDEEP
system-verilog
user2400361
user2400361

Reputation: 169

do system verilog parameters reduce simulation speed

Does using system verilog parameters in RTL instead of constants reduce simulation speed in any way? One of my 'influential' colleagues is claiming so. It doesn't make sense to me because aren't parameters essentially constants in the simulation binary executable?

Upvotes: 0

Views: 334

Answers (2)

dave_59
dave_59

Reputation: 42738

It may depend on which simulator you are using and how you are using it. Modelsim/Questa has a flow when you want to run many simulations of the same design with different parameter values, and the compilation time for each simulation takes a significant amount of time relative to the run time. In that flow, you can "float" the parameters which will prevent certain optimizations from happening. Then as you run each simulation, you can override those parameters from the command line. If you are not using that flow, then they are just constants that get optimized away.

Upvotes: 0

dwikle
dwikle

Reputation: 6978

Parameters are resolved at compile/elaboration time so they should not affect simulation speed.

I suppose that heavy use of parameters for parameterizing classes could have an impact if the size of the binary image was so large that the simulator had issues with it. However I have never heard anyone raise this concern.

Upvotes: 1

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