calculation of simulation time in verilog

Question

I want to calculate the simulation time of a calculation of one prime number, which is the number of clock cycle to calculate one prime number. As we know, the calculation of a large prime number takes more clock cycles than a small prime number.

I used $time in Verilog whenever a prime is calculated and captured it in a time_s register. I calculated the difference of calculation after another prime number. Here is my code where you can see time_s1 captured the time when a prime is calculated. time_s2 is the time to calculate the difference.

module prime_number_count(
  input clk
);

//for count 1
parameter N =100;          // size of array
parameter N_bits = 32;
reg     [N_bits-1:0] prime_number[0:N-1]; // memory array for prime_number 
reg     [N_bits-1:0] prime_aftr50 [0:49]; // memory array to get       
integer     k;               // counter variable   
integer     k1;               // counter variable   
integer     count;  
integer     test;
integer     time_s1;
integer     time_s2;
integer      check; //Counts 1 to k
localparam S_INC   = 2'b01;
localparam S_CHECK = 2'b10;
reg [1:0] state;

initial begin
 prime_number[0] = 'd1;
 prime_number[1] = 'd2;
  //prime_aftr50[0] = 'd0;
  state           = S_CHECK; //Check set count first
  count           = 'd3;
  k               = 'd2; //0,1 preloaded
  check           = 'd1;
  test            = 'd1;
   time_s1            = 'd0;
   time_s2            = 'd0;
     k1               = 'd0;
end

always @(posedge clk ) 
 begin

         $display ("time of clock   %d ", $time );
        if(state == S_INC)
        begin  // if state is 1
          //$display("State: Incrementing Number to check %d", count+1);
          count <= count+1 ;
          state <= S_CHECK ;           // chang the state to 2
          check <= 'd1; // Do not check against [0] value 1
          test  <= 'd1; // Safe default
        end     

        else if (state == S_CHECK) begin
             if (test == 0) begin
             // Failed Prime test (exact divisor found)
              $display("Reject        %3d", count);
              state           <= S_INC ;
             end
             else 
            if (time_s2>30000)begin
             prime_number[k]=prime_number[k-1];
             time_s1         <=$realtime ;
         state           <= S_INC ;     
             k               <=  k + 1;              
             $display("Found %1d th Prime_1 %1d", k, count);
             $display("display of simulation time" , time_s2);
             end // end of simulation time
             else 

                    if (check == k) begin
                      //Passed Prime check
                      time_s1         <=$time ;
                      prime_number[k] <=  count;
                      k               <=  k + 1;
                      state           <= S_INC ; 
                      $display("Found %1d th Prime_1 %1d", k, count);
                      $display("display of simulation time" , time_s2);
                      end

             else begin
             //$display("Check");
             test  <= count % prime_number[check] ;
             check <= check + 1;
             //$display("Checking %1d against %1d prime %1d : %1d", count, check, prime_number[check], count % prime_number[check]); 
             end
      end
end     
 ////////////////////////////////////////////////////////////////// 
always @(posedge clk )
begin 
     if(check==k-1)
     begin
     time_s2 <=$realtime-time_s1;
    // $display("display of simulation time" , time_s2) ;
     end
 end

always @ (posedge clk) begin
  if ( k==51+(50*k1)) begin
    prime_aftr50[k1] <= count;
    k1               <= k1+1;   
  end               
end

endmodule

Answer 1

Background on time

Semantically I would recommend using time over integer, behind the scenes they are the same thing. But as it is only an integer it is limited to the accuracy of the timescale time_unit*. Therefore I would suggest you actually use realtime which is a real behind the scenes.

For displaying time %t can be used instead of %d decimal of %f for reals. The formatting of this can be controlled through $timeformat.

realtime capture = 0.0;
//To change the way (below) is displayed
initial begin
  #80.1ns;
  capture = $realtime;
  $display("%t", capture);
end
 

To control how %t is displayed :

//$timeformat(unit#, prec#, "unit", minwidth);
$timeformat(-3, 2, " ms", 10);    // -3 and " ms" give useful display msg
 
unit      is the base that time is to be displayed in, from 0 to -15
precision is the number of decimal points to display.
"unit"    is a string appended to the time, such as " ns".
minwidth  is the minimum number of characters that will be displayed.
 
unit:  recommended "unit" text
  0 =   1 sec
 -1 = 100 ms
 -2 =  10 ms
 -3 =   1 ms 
 -4 = 100 us
 -5 =  10 us
 -6 =   1 us 
 -7 = 100 ns
 -8 =  10 ns
 -9 =   1 ns 
-10 = 100 ps
-11 =  10 ps
-12 =   1 ps 
-13 = 100 fs
-14 =  10 fs
-15 =   1 fs 

With these changes: realtime types, $realtime captures and displaying with %t analysing simulation time becomes a little easier.

Solution

Now to calculate the time between finding primes:

Add to your the following to intial begin:

$timeformat(-9, 2, " ns", 10); 

Then in the state which adds the prime to the list you just need to add the following:

          //Passed Prime check
          time_s2         = time_s1; //Last Prime
          time_s1         = $realtime ;
          $display("Found %1d th Prime_1 %1d", k, count);
          $display("Found at time : %t", time_s1);
          $display("Time Diff      : %t", time_s1 - time_s2);

Working example on EDA Playground.

timescale

*: time scales for verilog simulations are set by, the time_unit sets the decimal point so any further accuracy from the precision is lost when using time or integer to record timestamps.

`timescale <time_unit>/ <time_precision>

See section 22.7 of IEEE 1800-1012 for more info.

Updated link to SystemVerilog Standard 1800 IEEEE Design Automation Standards