CODEWITHSUNDEEP
c++hardwareverilogfpgahdl
StuckInPhDNoMore
StuckInPhDNoMore

Reputation: 2679

Can I find the execution time of verilog code?

I know that verilog is an HDL and its all about parallel processing but the problem I face is that I have to write a report on why a section of C++ code is better in an HDL environment.

So I have the C++ code, which I wrote in Verilog. It works perfectly. Now I have to write a report on how this section of code is faster in Verilog. So I have to do execution time comparisons.

I managed to find the execution time of my C++ code using the following method:

#include <iostream.h>
#include <time.h>
using namespace std;


int main()
{
    clock_t t1,t2;
    t1=clock();
    //code goes here
    t2=clock();
    float diff ((float)t2-(float)t1);
    cout<<diff<<endl;
    system ("pause");
    return 0;

}

Now how can I get the same result in Verilog? Is there any option in the Xilinx compiler that can tell me how long this code will take to produce the end result after it has been programmed onto an FPGA board? or can I add something to the code that will be able to give this result?

Thank you

Upvotes: 0

Views: 3715

Answers (3)

Serge
Serge

Reputation: 12344

Verilog is about describing behavior of hardware. A verilog simulator is to simulate the description on a computer. A verilog emulator is to emulate the behavior implementation in fpgas.

In any case the simulation or emulation take multiple cycles. Your C++ program takes only '1' cycle. So, first of all you have to make it to run for multiple cycles, providing change in clocks. Something like this:

for (int i = 0; i < MAX_CYCLES; i++) {
    myClk = ~ myClk;
    executeMyCode(myClk);
}

for verilog simulations you would need something like that to toggle clocks:

initial begin
    for (int i = 0; i < MAX_CYCLES; i++) begin
        #1 myClk= ~myClk
    end
    $finish;
end

you cannot synthesize the above in fpgas, so for emulation you would need to play with clocks and tell the emulator for how long to run (MAX_CYCLES?), make sure that the clock changes as many times as in c++ or simulation.

verilog simulation does never run in parallel on a computer. It just pretends to do so by altering evaluation order of different parts of the model.

Emulation does real parallelism based on the hardware implementation.

Depending on the nature of the code you might find that c++ is better :-).

Upvotes: 1

user1619508
user1619508

Reputation:

I think you are missing the point entirely. You don't execute programs in Verilog, you design hardware with it. It's a hardware description language. Running a simulation of your Verilog and using the $time or $realtime commands will tell you nothing about how long it actually takes for your algorithm to run in hardware.

What you need to do is synthesize your Verilog to an FPGA, then look at the synthesis reports to see how long it will take from a change in the algorithm inputs until the output(s) are valid. Of course, you may need to add pipelining or use synthesis constraints to get a decent result from synthesis. This is not a trivial process, so expect to spend time learning how it is done and done well.

Upvotes: 5

DOS
DOS

Reputation: 557

I think what you are looking for is this: $time

Here is a quick example: http://www.asic-world.com/verilog/vbehave2.html example

Upvotes: 1

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