CODEWITHSUNDEEP
statisticstimingverilogxilinxmodelsim
node ninja
node ninja

Reputation: 32986

How to measure the timing of a Verilog module in Modelsim or Xilinx ISE Project Navigator

I designed a 4-bit Carry Look-ahead Adder using half-adder modules. Then I designed another 4-bit Carry Look-Ahead adder using functional Verilog description. The second one is supposed to be faster. How can I verify this? Is there a way to see how fast a module functions in either Modelsim or Xilinx ISE Project Navigator?

Upvotes: 0

Views: 530

Answers (1)

Andy
Andy

Reputation: 4866

To get a summary timing report in ISE, you can run "Implement Design > Place & Route > Generate Post-Place & Route Static Timing". Then go to "Design Summary > Detailed Reports > Post-PAR Static Timing Report".

This will show you at least the slowest path in your design and the overall speed. If you need more detail you can look at the ISE Timing menu, or look at the "trce" command line tool.

Upvotes: 1

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