CODEWITHSUNDEEP
c++gccmakefile
MERM
MERM

Reputation: 752

Makefile using mixed versions of gcc

I just installed gcc 4.8 via brew on my OSX (Snow Leopard) Machine.

When I run make it uses the old version of g++ for the object file and the new version for the executable. 

$ make
g++    -c -o myprogram.o myprogram.cc
g++-4.8 -g -Wall -o myprogram myprogram.o

I'm sure it is a simple thing in my Makefile, can anyone help me correct this?

Makefile:

CC        := g++-4.8
CFLAGS    := -g -Wall

SRCS      := myprogram.cc
OBJS      := ${SRCS:.cc=.o}
TARGET    := ${SRCS:.cc=}

default: all

all: $(OBJS)
    $(CC) $(CFLAGS) -o $(TARGET) $(OBJS)

Here is the version info: 

$ g++ --version
i686-apple-darwin10-llvm-g++-4.2 (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2336.1.00)
Copyright (C) 2007 Free Software Foundation, Inc.

$ g++-4.8 --version
g++-4.8 (GCC) 4.8.1
Copyright (C) 2013 Free Software Foundation, Inc.

Upvotes: 2

Views: 3989

Answers (2)

Slava
Slava

Reputation: 44268

First of all your make file seems to be incorrect and only works because you have one source file. When you will try to add more files to SRCS it will break (there will be multiply parameters passed after -o). Usually you specify TARGET explicitly as program name, not source files without extension. You specified only one rule to link your executable:

all: $(OBJS)
    $(CC) $(CFLAGS) -o $(TARGET) $(OBJS)

Which is also not quite correct, it should be:

$(TARGET): $(OBJS)
    $(CC) $(CFLAGS) -o $(TARGET) $(OBJS)

You can add dependency on all:

all: $(TARGET)

Now you did not specify rule on how to build .o file from .cc but make is clever enough to have implicit rule for you. But for c++ programs make uses CXX variable, not CC (you should follow that as well) thats why you do not have g++-4.8 on compile. So more proper file could look like this:

CXX       := g++-4.8
CXXFLAGS  := -g -Wall

SRCS      := myprogram.cc
OBJS      := ${SRCS:.cc=.o}
TARGET    := myprogram

.PHONY: default all

default: all

all: $(TARGET)

$(TARGET): $(OBJS)
    $(CXX) $(CXXFLAGS) -o $(TARGET) $(OBJS)

%.o: %.cc
    $(CXX) $(CXXFLAGS) -c -o $@ $<

%.o: %.c may not be necessary but to show how implicit rules work. To provide it explicitly would not hurt.

PS I added explicit -o parameter to the last rule. I just used the fact that g++ will generate .o file by default and "-o filename.o" can be omitted with the same result.

Upvotes: 2

Carl Norum
Carl Norum

Reputation: 225132

You're using make's default rules to build your object files. Since your source file is C++ (as indicated by the .cc extension), you need to override the CXX and CXXFLAGS variables in addition to the CC and CFLAGS variables you're using for the link step. Something like these should do it:

CXX := $(CC)
CXXFLAGS := $(CFLAGS)

Upvotes: 3

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