CODEWITHSUNDEEP
verilogsystem-verilog
Hemant Bhargava
Hemant Bhargava

Reputation: 3585

Verilog syntax for declaring a wire

Is this a legal declaration in Verilog?

wire \n_628_B[-1111111109] ;

Upvotes: 1

Views: 1373

Answers (2)

toolic
toolic

Reputation: 62236

As odd as it might seem, that is legal syntax. Refer to IEEE Std 1800-2012, Section 5.6.1 "Escaped identifiers". The following code is legal:

module tb;

wire \n_628_B[-1111111109] ;
reg foo;

assign \n_628_B[-1111111109] = foo;

initial begin
    $monitor(\n_628_B[-1111111109] );
    foo = 1;
    #5 foo = 0;
end

endmodule

Output:

1
0

Because it is so odd, I strongly recommend against using it, if you have a choice.

Upvotes: 4

CliffordVienna
CliffordVienna

Reputation: 8255

Yep. Everything after a backslash and before the next whitespace is an identifier in Verilog. So the part in square brackets is not an array size or anything but just part of the signal name. Auto-generated Verilog code (for example verilog netlists) contains such escaped identifiers all the time. I personally would not use it in hand-written code though.

Upvotes: 2

Related Questions