CODEWITHSUNDEEP
for-loopvhdlsynthesis
MSD
MSD

Reputation: 129

Synthesising FOR-GENERATE in VHDL

I am using FOR-GENERATE and IF-GENERATE in VHDL program.Is these commands are synthesizable? What are the advantages and disadvantages of these commands. Can we use FOR-GENERATE inside IF-GENERATE? Because when I am using FOR-GENERATE inside IF-GENERATE then it is creating an error

Upvotes: 1

Views: 1317

Answers (1)

user2778477
user2778477

Reputation:

Is these commands are synthesizable?
Yes, they're synthesizable if you use them correctly.

advantages and disadvantages of these commands
For advantages, GENERATE statement makes it easy to create wellpatterned structures. For disadvantages, see @BennyBarns's comment below.

Can we use FOR-GENERATE inside IF-GENERATE?
Any VHDL concurrent statement can be included in a GENERATE statement, including another GENERATE statement.

[LRM93 $9.7]

generation_scheme ::=
for generate_parameter_specification
| if condition

With the FOR scheme
1.All objects created are similar.
2.Loop cannot be terminated early.

With the IF scheme
1.Allows for conditional creation of components.
2.Can’t use ELSE or ELSIF clauses.

Upvotes: 2

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