CODEWITHSUNDEEP
vhdl
Mac
Mac

Reputation: 111

FSM with Structural Description

Using FSM in VHDL you have to declare the states, that are going to be used:

 type state_values is (ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST8,ST9,ST10,ST11,ST12,ST13,ST14,ST15,ST16);
   signal pres_state, next_state: state_values;

I've tried used the states as a LOGIC_VECTOR, but then the state definition wouldn´t be necessary. When using a Structural implementation, is there a way to use the state definition betweeen the components? Is there a way to implement a FSM with components?

Upvotes: 0

Views: 175

Answers (1)

user1818839
user1818839

Reputation:

Declare your state type in a package, then you can use the package in both components and they will share the state type; you can interconnect them with signals and ports of that type, etc.

But my question is why? The single process form of state machine is generally simpler and more reliable (it has just "state" instead of "present_state" and "next_state"). What purpose is there in splitting a SM into not just several processes, but several components?

Upvotes: 3

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