CODEWITHSUNDEEP
cmakefile
bph
bph

Reputation: 11268

Makefile use of $<

Can anyone explain why the use of $< in:

$(BUILD_DIR)/release/%.o: %.c $(HEADERS)
    $(RELEASE_LINK.c) $< -c -o $@

iterates over both the .o files and .c files in pairs building an obj file from a c file, whereas $< in:

$(program_C_OBJS) : $(program_C_SRCS)
    $(RELEASE_LINK.c) $< -c -o $@

iterates over all the obj files but only ever pulls out the 1st dependency, i.e. the 1st c file

Is it possible in the 2nd example to modify such that the matching pairs of obj and c files are built as happens in the 1st example?

Upvotes: 0

Views: 123

Answers (2)

Olaf Dietsche
Olaf Dietsche

Reputation: 74098

From GNU Make - 10.5.3 Automatic Variables

$<
The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule

Depending on what you want to accomplish, there is also

$?
The names of all the prerequisites that are newer than the target, with spaces between them.
$^
The names of all the prerequisites, with spaces between them

You can build a specific set of objects by stating them as dependencies to another target 

target1: $(program_C_OBJS)

Now, when you call 

make target1

make tries to create the dependencies for target1, which in turn can be built using your first rule, one by one. Of course, you can specify a command for target1 as well. This command will be executed as soon as its dependencies $(program_C_OBJS) are built.

Upvotes: 1

Etan Reisner
Etan Reisner

Reputation: 81042

The $< variable doesn't "iterate" anything. It doesn't do anything but expand to the name of the first prerequisite of the target it is expanded in.

The first rule is a pattern rule. It applies to any files that need to be built that match that pattern.

The second rule (which almost certainly doesn't do anything even remotely like what you want unless those variables contain patterns) maps specific output files to specific input files (in your case presumably the limited set of input C files you want the rule to apply to).

The choice about what files get compiled during any given make run is determined by what files make is told to build and which of their dependencies make determines need to be updated to make that happen.

Upvotes: 1

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