CODEWITHSUNDEEP
assemblymips
VAK5d6
VAK5d6

Reputation: 47

Nop and Pipeline Hazards in this Assembly MIPS

After Compiling C to Assembly MIPS by Cross Compiler , i had:

main:
.frame $fp,32,$31 # vars= 16, regs= 1/0, args= 0, gp= 8

addiu $sp,$sp,-32
sw $fp,24($sp)
move $fp,$sp
li $2,5 # 0x5
sw $2,8($fp)
lw $2,8($fp)
nop
sw $2,16($fp)
li $2,5 # 0x5
lw $3,16($fp)
nop
beq $3,$2,$L4
nop

li $2,10 # 0xa
lw $3,16($fp)
nop
beq $3,$2,$L5
nop

li $2,1 # 0x1
lw $3,16($fp)
nop
beq $3,$2,$L3
nop

b $L7
nop

$L3:
lw $2,8($fp)
nop
addiu $2,$2,3
sw $2,8($fp)
b $L7
nop

$L4:
lw $2,8($fp)
nop
sll $2,$2,3
sw $2,8($fp)
b $L7
nop

$L5:
lw $2,8($fp)
nop
srl $2,$2,2
sw $2,8($fp)
$L7:
move $sp,$fp
lw $fp,24($sp)
addiu $sp,$sp,32
j $31
nop

.end main

I don't understand why there are many nop code lines, what is the meaning of nop in this code ? does it help anything in Pipeline Hazards? What if i remove all the nops ?

Upvotes: 3

Views: 6875

Answers (2)

Filipe Gonçalves
Filipe Gonçalves

Reputation: 21213

NOPs were inserted due to pipeline hazards.

Recall that MIPS pipeline is composed of 5 stages: Fetch, Decode, eXecute, Memory, Write-back.

Let's go through some NOPs. The first one is:

lw $2,8($fp)
nop
sw $2,16($fp)

This code assumes there is no Memory-Memory forwarding. Why? Because if you draw a time-line pipeline diagram, you will see that the NOP is forcing sw's Memory stage to occur exactly one cycle after the write-back stage on lw. Thus, the code assumes that the processor has Memory -> ALU forwarding, or Write-back -> Memory forwarding. Had we not used a NOP in between, sw's Memory stage would read some garbage value from $2 (whatever came from the decode stage), and the behavior would be undefined.

The second nop:

lw $3,16($fp)
nop
beq $3,$2,$L4

Here, $3 is only available after lw's Memory stage is finished. If we don't have a NOP, then beq eXecute stage would occur in the same cycle as lw's Memory stage, which is not possible even with Memory -> ALU forwarding. Therefore, we have to delay beq for one cycle, and that's what NOP is doing. With this NOP, beq's eXecute stage will occur one cycle after lw's Memory. This works, assuming there is Memory -> ALU forwarding.

Similar reasons apply to the other cases, I suggest trying to figure them out by yourself.

Upvotes: 2

user2760375
user2760375

Reputation: 2558

according to your code all 'nop' instructions are added to fix the following error

1) branch delay

2) load delay

as these nop are added by compiler you can explicitly give an option to compiler to not add these nop instruction by "set noreorder" better I should give you reference to read . "See Mips Run 2nd Edition" page no. 288. And I don't see 'nop' is hazard barrier inst. as according to this book.

Upvotes: 2

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