CODEWITHSUNDEEP
assemblymipscpu-architecture
Giacomo Benso
Giacomo Benso

Reputation: 107

WAR hazard causes bubbles in the pipeline (MIPS)?

If I have 2 lines of assembly like:

add $s1, $s3, $s5 
sub $s3, $s6, $s8

this should cause a WAR (write after read) hazard, correct?

The problem is that I do not understand if it will cause the insertion of bubbles in the pipeline since I have to draw the pipeline table.

Is there any different case when this can cause a hazard or not?

Upvotes: 0

Views: 364

Answers (1)

Patrick Roberts
Patrick Roberts

Reputation: 51866

WAR hazard is uncommon/impossible in a reasonable (in-order) pipeline

Pipeline Hazards, Page 2

Here's a table to demonstrate why, in a 5-stage pipelined CPU. Let's label them instructions 1 and 2.

 IF | ID | EX | MEM | WB
-------------------------
 1  |    |    |     |
-------------------------
 2  |(1) |    |     |     Instruction 1 is obtaining $s3
-------------------------
    | 2  | 1  |     |    
-------------------------
    |    | 2  |  1  |
-------------------------
    |    |    |  2  | 1
-------------------------
    |    |    |     |(2)  Instruction 2 is writing $s3 back

Instructions obtain operands from the register file during the ID (Instruction Decode) stage, but the result isn't written back to the register file until the WB (write-back) stage. Instruction 1 is in the ID stage 4 clock cycles before instruction 2 is in the WB stage, so there is no possibility of $s3 being overwritten before it is used.

Upvotes: 4

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