Place:1108 error in VHDL (Help)

Question

I am designing a simple combination lock design in VHDL on a Spartan 6 FPGA. This error has come up and i am a bit confused to how i could fix it. I have "googled" this and according to this answer in this thread Too many comps of type “BUFGMUX” found to fit this deviceI beleive i know the problem but i am unsure how to solve it.

Now correct me if i am wrong but i believe this error came about due to the following code in my design

--clock divider
process(cclk,clr)
begin   
    if (clr ='1') then
        Count200Hz <= X"00000";
        --clk200     <= '0';
        temp       <= '0';
    elsif rising_edge(cclk) then
        if (Count200Hz = clk200HzEndVal) then
            clk200     <= not temp;
            Count200Hz <= X"00000";
        else
            Count200Hz <= Count200Hz + '1';
        end if;
    end if;
end process;

-- 2-bit counter
process(cclk,clr)
begin
    if clr = '1' then
        s <= "00";
    elsif rising_edge(cclk) then
        s <= s+1;
    end if;
end process;

--state machine
    state_mach:PROCESS(lclk, clr)
    BEGIN
        IF clr = '1' THEN
            present_state <= idle;
        ELSIF rising_edge(lclk) THEN
            present_state <= next_state;
        end if;
    END PROCESS;

    pulse_process: process(cclk, rst)
    begin
        if rst = '0' then
            pulse <= '0';
            count <= 0;
            current_state <= idle;
        elsif (rising_edge(cclk))then
            current_state <= next_state;
....

These code are from different vhdl modules in my design. does the ise believes that there are three different clock used in my design hence why the error is thrown??

The thing is that they are different clock but they stem from the systems clock ones the clock at an lower frequency, one is the clock pulse. I have added my top-level design for some clarity

Any help is appreciated

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity simpleLock_top is
Port ( 
    mclk  : in   STD_LOGIC;
    rst   : in   STD_LOGIC;
    btnl  : in   STD_LOGIC;
    btnr  : in   STD_LOGIC;
    sw    : in   STD_LOGIC_VECTOR (3 downto 0);
    seg7  : out  STD_LOGIC_VECTOR (6 downto 0);
    an    : out  STD_LOGIC_VECTOR (3 downto 0);
    led   : out  STD_LOGIC_VECTOR (7 DOWNTO 0);
    dp    : out  STD_LOGIC);
    end simpleLock_top;

architecture Behavioral of simpleLock_top is

component x7seg_msg is
Port ( 
    x    : in   STD_LOGIC_VECTOR (15 downto 0);
    cclk : in   STD_LOGIC;
    clr  : in   STD_LOGIC;
    seg7 : out  STD_LOGIC_VECTOR (6 downto 0);
    an   : out  STD_LOGIC_VECTOR (3 downto 0);
    dp   : out  STD_LOGIC);
end component;

component clkdiv is
Port (
    cclk   : in  STD_LOGIC;
    clr    : in  STD_LOGIC;
    clk200 : out STD_LOGIC);
end component;

component simpleLock is
PORT (
    lclk   : IN  STD_LOGIC;
    clr   : IN  STD_LOGIC;
    btnl  : IN  STD_LOGIC;
    btnr  : IN  STD_LOGIC;
    code  : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
    sw    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
    led   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    digit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    user_input : OUT STD_LOGIC_VECTOR(15 downto 0));
end component;

component clock_pulse is
PORT ( 
    cclk  : IN  STD_LOGIC;
    rst   : IN  STD_LOGIC;
    trig  : IN  STD_LOGIC;
    pulse : OUT STD_LOGIC);
end component;

constant code : STD_LOGIC_VECTOR(15 downto 0):= X"1234";
signal digit: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal user_input : std_logic_vector(15 downto 0);
signal clk200, clkp, btn01: STD_LOGIC;
signal btn : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
    btn(0) <= btnr;
    btn(1) <= btnl;
    btn01  <= btn(0) or btn(1);
    --led <= X"00";

    V1: clkdiv
        port map(
            cclk   => mclk,
            clr    => rst,
            clk200 => clk200);

    V2: x7seg_msg
        port map(
            x    => user_input,
            cclk => clk200,
            clr  => rst,
            seg7 => seg7,
            an   => an,
            dp   => dp );

    V3: simpleLock
        port map(
            lclk  => clkp, 
            clr   => rst, 
            btnl  => btnl,
            btnr  => btnr,
            code  => code,
            sw    => sw,
            led   => led,
            digit => digit,
            user_input => user_input);

    V4: clock_pulse
        port map(
            cclk  => clk200,
            rst   => rst,
            trig  => btn01,
            pulse => clkp);
end Behavioral;

Answer 1

Clock Enable

In an FPGA design, it is often better to use the less possible different clocks.

If your "clock_pulse" module generate a one cycle clock pulse, don't use this pulse as a clock ('clkp' in your code), but as a clock enable ('enable' in the code below).

myproc : process(clk, rst)
begin
  if rst = '1' THEN
    -- your asynchronously reseted signals
  elsif rising_edge(clk) THEN
    if enable = '1' then
      -- things that must be done when you get the one cycle pulse
    end if;
  end if;
end process;

But take care of any unmanaged clock domain crossing...

Hope this helps.