CODEWITHSUNDEEP
makefile
borges
borges

Reputation: 3687

How can I pass all command line arguments to a program in a Makefile?

I can do:

all:
    $(CC) -DFOO=$(FOO) -DBAR=$(BAR) main.c

And call it with:

make FOO=foo BAR=bar

But I want a more generic solution in a way that I don't have to write ALL possible variables in the compiler call line. I know, for example, that MAKECMDGOALS variable has all targets from the command line. There is any MAKECMDVARS-like variable that contains all variables from command line? So I could do something like this:

CONFIGS = $(addprefix -D, $(MAKECMDVARS))

all:
    $(CC) $(CONFIGS) main.c

Upvotes: 0

Views: 123

Answers (1)

MadScientist
MadScientist

Reputation: 100836

In my opinion this is a bad idea. It will break everyone's understanding of how make works, and it will mean you can't use variable overrides for their intended purpose. What if you want to change CC for just a single build using make? Or CFLAGS? Or some other variable?

However, if you really want to do it you can: all variables assigned on the command line are put into the -*-command-variables-*- variable:

$ echo 'all: ; @echo variables: $(-*-command-variables-*-)' | make -f-
variables:

$ echo 'all: ; @echo variables: $(-*-command-variables-*-)' | make -f- FOO=foo BAR=bar
variables: BAR=bar FOO=foo

Upvotes: 2

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