Reputation: 1025
I want to specify some command line parameters in a makefile. I normally run my program like
this:
gcc -o prog prog2.c prog.c
./prog text1.txt text2.txt
Makefile:
prog: prog2.o prog.o
gcc -o prog prog2.o prog.o
prog2.o: prog2.c prog2.h
gcc -c prog2.c
clean :
rm prog2.o
How do I include the txt files here?
Also how do I give executions in a single make file. Say if I also want to run
gcc -o prog prog3.c prog.c
./prog text1.txt text2.txt
Upvotes: 2
Views: 19681
Reputation: 753705
test: prog
./prog text1.txt text2.txt
Or:
TEST_FILES = text1.txt text2.txt
test: prog
./prog ${TEST_FILES}
Upvotes: 1
Reputation: 385600
Make a run
target:
.PHONY: run
run: prog
./prog text1.txt text2.txt
prog: prog2.o prog.o
gcc -o prog prog2.o prog.o
# etc.
Then you can say make run
, or just make
if run
is the first target in the Makefile
.
Upvotes: 7