CODEWITHSUNDEEP
integercomparisonvhdl
user3237992
user3237992

Reputation: 133

integer comparison doesn't work in if statement (vhdl)

What is the error in the following code?

In the testbench x is set to "00001111", yet the else branch is executed (in the simulation all of y's bits are set to high impedance state, but y should equal x). I'm using XILNX ISE Design Suite and ISim as simulation environment. Thanks in advance.

entity test is
    Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end test;

architecture Behavioral of test is

signal tmp : integer;

begin

process(x)
begin
tmp <= to_integer(unsigned(x(3 downto 0)));
if tmp = 15 then
    y <= std_logic_vector(to_unsigned(tmp, 8));
else
    y <= "ZZZZZZZZ";
end if;
end process;

end Behavioral;

Upvotes: 1

Views: 16742

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The tmp is a signal, thus it takes a delta delay before it reveals the value assigned by (pkg_sig_1'range) <= z(pkg_sig_1'range);. So when the process is triggered at the change of x, the tmp will have the previous value in the if tmp = 15 then ..., and the new value of tmp is not assigned until after the process is completed.

Add tmp to the sensitivity list, or change tmp to a variable in the process, like:

process(x)
  variable tmp : integer;
begin
  tmp := to_integer(unsigned(x(3 downto 0)));
  if tmp = 15 then
    y <= std_logic_vector(to_unsigned(tmp, 8));
  else
    y <= "ZZZZZZZZ";
  end if;
end process;

Upvotes: 2

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