CODEWITHSUNDEEP
system-verilog
e19293001
e19293001

Reputation: 2911

SystemVerilog array random seed of Shuffle function

I get the same output everytime I run the code below.

module array_shuffle;
   integer data[10];

   initial begin
      foreach (data[x]) begin
         data[x] = x;
      end

      $display("------------------------------\n");
      $display("before shuffle, data contains:\n");

      foreach (data[x]) begin
         $display("data[%0d] = %0d", x, data[x]);
      end

      data.shuffle();
      $display("------------------------------\n");
      $display("after shuffle, data contains:\n");

      foreach (data[x]) begin
         $display("data[%0d] = %0d", x, data[x]);
      end

   end
endmodule

Output:

------------------------------

before shuffle, data contains:

data[0] = 0
data[1] = 1
data[2] = 2
data[3] = 3
data[4] = 4
data[5] = 5
data[6] = 6
data[7] = 7
data[8] = 8
data[9] = 9
------------------------------

after shuffle, data contains:

data[0] = 8
data[1] = 6
data[2] = 7
data[3] = 9
data[4] = 5
data[5] = 0
data[6] = 1
data[7] = 4
data[8] = 2
data[9] = 3

Is there a way to seed the randomization of the shuffle function?

Upvotes: 2

Views: 9860

Answers (1)

Tudor Timi
Tudor Timi

Reputation: 7573

Shuffle returns the same result every time because you probably run the simulator with the same seed. This is the intended behavior, because when you run a simulation and find a bug, you want to be able to reproduce it, regardless of any design (and to some extent testbench) changes. To see a different output, try setting the seed on the simulator command line. For Incisive this is:

irun -svseed 1    // sets the seed to 1
irun -svseed random   // will set a random seed

It's also possible to manipulate the seed of the random number generator using set_randstate, but I wouldn't mess with that.

Upvotes: 4

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