CODEWITHSUNDEEP
verilogsystem-verilog
sara8d
sara8d

Reputation: 433

How to randomize an array of bit arrays in verilog?

I am new to Verilog.

How can I randomize the following:

 bit [7:0] data [];

*Without use randomize() of systemVerilog.

Upvotes: 3

Views: 6621

Answers (2)

dave_59
dave_59

Reputation: 42788

SystemVerilog will not change the size of a dynamic array unless you put a constraint on it. So you either need to allocate the array before calling randomize(), or use a constraint to randomize the size.

bit [7:0] data [];

data = new[10];
randomize(data);

or

bit [7:0] data [];

randomize(data) with {data.size inside {[5:15]} ;};

or if you do not have access to the randomize() SystemVerilog, you can do 

  data = new[10];
  foreach(data[ii]) data[ii] = $urandom;

Upvotes: 4

Rahul Menon
Rahul Menon

Reputation: 792

constrain the size of the array to the required range and call randomize. It should generate an array with random data ( in the example below of size between 30 and 40 ) 

class rand_gen ;

rand bit [7:0]   data[];
constraint db { data.size inside  {[30:40]}; }

task generate ();
 randomize(data);
end task

endclass

Upvotes: 2

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