Reputation:
I have a Makefile building many C files with long long command lines and we've cleaned up the output by having rules such as:
.c${MT}.doj:
@echo "Compiling $<";\
$(COMPILER) $(COPTS) -c -o $@ $<
Now this is great as the @ suppresses the compilation line being emitted. But when we get an error, all we get is the error message, no command line. Can anyone think of a "neat" way to emit the command line? All I can think of doing is echoing it to a file and have a higher level make catch the error and cat the file. Hacky I know.
Upvotes: 5
Views: 11364
Reputation: 452
This question is pretty old, but for those of you Googling, I think what I’ll do in this situation is alias make
to make -s
(silent mode) in my shell, and only put the @
prefix before lines where echo
or other diagnostic commands are being invoked. When I want the full output from make
, I will override my alias by calling it as \make
.
Also note that in this situation that you’ll need to do the typical thing and put the @echo
on its own line, with the actual rule commands on separate lines and without @
’s.
Upvotes: 7
Reputation: 6805
Tested and it worked (GNU make in Linux):
.c${MT}.doj:
@echo "Compiling $<";\
$(COMPILER) $(COPTS) -c -o $@ $< \
|| echo "Error in command: $(COMPILER) $(COPTS) -c -o $@ $<" \
&& false
Upvotes: 7
Reputation:
I recently used a utility called logtext for the likes of tracking what output had occurred during the course of a bat file executing. Check it out, you may find this pretty useful if you want to know what error occurred where.
Upvotes: 0
Reputation: 14051
A simple solution would be to use a simple script abc
like the following:
#!/bin/bash
$@
code=$?
if (( code )); then
echo error running $@
fi
exit $code
Then you can write abc $(COMPILER) $(COPTS) -c -o $@ $<
in your Makefile
. Do note that this does not work when you have pipes or redirects (as they will be applied to abc
instead of the command you want to run).
You can also just put similar code directly in the Makefile
if that's preferable.
Upvotes: 0