CODEWITHSUNDEEP
vhdl
ni9e
ni9e

Reputation: 161

Why not use only boolean

What are the reasons for using std_logic or std_ulogic instead of boolean?

std_logic can have other values than '1' and '0', but in an FPGA everything is resolved to either '1' or '0'. Doesn't this make simulations more unrealistic?

Upvotes: 3

Views: 3717

Answers (2)

Russell
Russell

Reputation: 3465

If you wanted to do a really good job, you would only use std_logic on your FPGA pins. You're right that once the signals in the FPGA, they are all resolved into either 0's or 1's. I have seen it done on some FPGA designs. Only the top level entity has std_logic type. Every other lower level component uses bit and bit_vector types. It makes your code as realistic as possible. However it does cause some headaches when trying to use anyone else's modules, because very few people do not use std_logic for their interfaces.

As another person already said, std_logic can be resolved into 'X', 'H', 'Z', etc, but these are only ever seen on FPGA interfaces.

Upvotes: 0

Karl-Henrik
Karl-Henrik

Reputation: 1113

A std_logic type can take on the following values:

• 'U': uninitialized. This signal hasn't been set yet. 
• 'X': unknown. Impossible to determine this value/result. 
• '0': logic 0 
• '1': logic 1 
• 'Z': High Impedance 
• 'W': Weak signal, can't tell if it should be 0 or 1. 
• 'L': Weak signal that should probably go to 0 
• 'H': Weak signal that should probably go to 1 
• '-': Don't care.

So far more than the bool that will not tell you that the signal was too weak or what it "probably" should be. So to answer your question the reason is that when using signal inputs you are hoping to get more information than just '0' or '1' should something not go according to design.

Reference to the std_logic_1164

Upvotes: 7

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