CODEWITHSUNDEEP
counterverilog
user3507563
user3507563

Reputation: 27

How can I show a sequence of numbers using a counter in Verilog

For example a have to show 0 , 2 , 4 , 0 , 2 , 4 .. I use an output with 8 segments - less important .

 output reg [7:0] data
 always @ (*) begin             
 case                                
 1:data= 8'b00000011; //number 0                        
 2:data= 8'b00100101; //number 2                     
 3:data= 8'b10011001; //number 4 
 default:data=8'b00000011;
 endcase
 end

And the counter :

input clock,
input reset,
output [7:0] out
reg [31:0] counter;
always @ (posedge clock) begin
if(reset==1)  counter <= 0;
else counter <= counter + 1;
end

My question is can I increment the case value instead of counter ? Like : 

always @ (posedge clock) begin
if(reset==1)  case <= 1;
else case <= case + 1;
if(case==3) reset<=1;
end

If not then how can I do this ?

Upvotes: 0

Views: 4338

Answers (1)

Ari
Ari

Reputation: 7556

Your case statement is wrong. It should select based on the counter value:

always @ (*) begin             
 case(counter)
  1: data= 8'b00000011; //number 0                        
  2: data= 8'b00100101; //number 2                     
  3: data= 8'b10011001; //number 4 
  default:data=8'b00000011;
 endcase
 end

Your counter should be:

always @ (posedge clock) begin
  if(reset==1 || counter == 3)  counter <= 1;
  else counter <= counter + 1;
end

Note that case is a keyword. You can't use it in an expression.

Upvotes: 3

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