CODEWITHSUNDEEP
system-verilog
user3472394
user3472394

Reputation: 71

Is reading of a clocking block output in system verilog allowed?

module input2 (output [3:0] out1, out2, input [3:0] in1, input clk);

clocking c_clk @(posedge clk);
output #2ns out1, temp = in1[1:0];
input in1;
endclocking

clocking d_clk @(posedge clk);
output out2;
input #2ns svar = in1[3:2];
endclocking

assign out1 = c_clk.temp ^ 4'b1101;
assign out2 = d_clk.svar + in1;

endmodule

My tool is giving an error:

Reading of a clocking block output (c_clk.temp ) is not allowed.

I have not found any standard for this statement. How can I solve this error?

Upvotes: 0

Views: 1056

Answers (1)

dave_59
dave_59

Reputation: 42788

The 1800-2012 standard says in 14.3 Clocking block declaration

It shall be illegal to read the value of any clockvar whose clocking_direction is output.

The reason is an output has no defined sampling semantics. An inout does.

Upvotes: 2

Related Questions