CODEWITHSUNDEEP
verilogsystem-verilog
Mana
Mana

Reputation: 83

Why Clocking block is not blocking?

Back to back assignment on interface signal using clocking block as blocking statement, but not working as expected.

For the below code I expect to set 1, but it is not set

Result:

At time 95: set to 1

then without waiting for clocking block, at timestamp 95, moved to the next statement to set 0.

Need help on this

interface intf(input clk);
   logic done;
   clocking smp_cb @(posedge clk); 
   endclocking
endinterface

module top;

   bit clk;
   always #5 clk =~clk;

   intf intf_inst(.*);

   initial begin
      repeat(10)@(posedge clk);
      $display("[%0t] set 1", $realtime);
      assign_intf(1);
      $display("[%0t] set 0", $realtime);
      assign_intf(0);
      //$display("[%0t] set 1", $realtime);
      //assign_intf(1);
      //$display("[%0t] set 0", $realtime);
      //assign_intf(0);
      repeat(10)@(posedge clk);
      $stop;
   end

   task assign_intf(logic val);
      intf_inst.done <= val;
      @( intf_inst.smp_cb);
      //@(posedge intf_inst.clk);
   endtask

   initial $monitor(" Monitor: [%0t] done_sig value %0d", $realtime, intf_inst.done);

endmodule

Upvotes: 0

Views: 667

Answers (1)

dave_59
dave_59

Reputation: 42788

Your problem is you should not be mixing event controls @(posedge clk) and clocking block events @(intf_inst.smp_cb) in the same process. If you intend on using a clocking block, your only interaction with signals should be through the clocking block. Otherwise you wind up with race conditions between the raw signals and the clocking block signals.

In your example, both events get triggered at the same time-step, but not simultaneously. At the point you call the assign_intf task, the clocking block event has not triggered yet.

Upvotes: 2

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