CODEWITHSUNDEEP
vhdl
user3653513
user3653513

Reputation: 13

Vhdl ERROR that I don't understand

I have a problem with my vhdl code . In active-hdl it works perfectly , but when i tried to implement it on the FPGA board using ise design xilinx i have a problem with one component . The error i found is:

ERROR:Xst:827 - "E:/proiect_final/dispozitiv_impartitor/src/generator_square_wave.vhd" line 16: Signal numar_intermediar<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity generator_square_wave is 
    port(clock,reset :in bit;
        controler:std_logic_vector(2 downto 0);
        numar:out std_logic_vector(7 downto 0);
        data_clock:out bit);
end generator_square_wave ;

architecture descriere of generator_square_wave  is
signal reset1:std_logic;
begin
        process (clock,reset) -- here it shows me the error 
        variable numar_intermediar:bit_vector(3 downto 0 ):="0000";
    variable numar_intermediar2:std_logic_vector(3 downto 0);
    variable bitul:bit;
    begin
        reset1<=to_stdulogic(reset);
            if rising_edge(reset1) then
                numar_intermediar:="0001";  
            numar_intermediar2:=To_StdLogicVector(numar_intermediar);
            numar(0)<=numar_intermediar2(0);
            numar(1)<=numar_intermediar2(1);
            numar(2)<=numar_intermediar2(2);
            numar(3)<=numar_intermediar2(3);
            numar(4)<='0';
            numar(5)<='0';
            numar(6)<='0';
            numar(7)<='0';

        else if( clock'event and clock ='1' and controler="001")then
                bitul:=numar_intermediar(0);
            numar_intermediar:=numar_intermediar srl 1;
            numar_intermediar(3):=bitul;
            numar_intermediar2:=To_StdLogicVector(numar_intermediar);
            numar(0)<=numar_intermediar2(0);
            numar(1)<=numar_intermediar2(1);
            numar(2)<=numar_intermediar2(2);
            numar(3)<=numar_intermediar2(3);
            numar(4)<='0';
            numar(5)<='0';
            numar(6)<='0';
            numar(7)<='0';
        if(reset/='1' and controler/="001")then
            numar<="00000000";
        end if;
    end if;
    end if;
            data_clock<=clock;
        end process;
end descriere;

Upvotes: 0

Views: 1457

Answers (1)

fru1tbat
fru1tbat

Reputation: 1625

You have a few problems. First, you shouldn't be treating reset as a clock (i.e. using rising_edge()). If it's asynchronous, you should just write:

if reset1 = '1' then
  ...

The following line also has a problem (not sure if this is strictly illegal, but it's not recommended):

if( clock'event and clock ='1' and controler="001")then

This should be:

if clock'event and clock = '1' then
  if controler = "001" then

(with additional end if to match.)

That should at least allow it to synthesize.

You may also want to make the statement reset1<=to_stdulogic(reset) concurrent instead of including it in the process, and there are a couple other possible changes you could make, but they're not as critical (unless I've missed something).

Upvotes: 1

Related Questions