CODEWITHSUNDEEP
makefile
Keisau CHING
Keisau CHING

Reputation: 103

Makefile: for-loop in a rule inside of a function

To make things simple, focus on the following example:

define FOO

test:
    @for str in a b c d ; do \
        echo $$str; \
    done;

endef

$(eval $(call FOO))

And I suppose when I entered

make test

I will get

a
b
c
d

(this is what I get if the rule is not defined in a function)

but unfortunately it gives me

tr
tr
tr
tr

I want my makefile gives me the previous(correct) result. Please help.

Moreover, I need to work with function to generate make rules. There have already been many existing rules in the actual makefile and I don't want to take a completely different way to do this if possible.

Upvotes: 1

Views: 718

Answers (1)

MadScientist
MadScientist

Reputation: 101111

You have to add more escaping, unfortunately. The end result you want is $$ in the rule, but the call function expands its argument, so you need:

define FOO

test:
        @for str in a b c d ; do \
            echo $$$$str; \
        done;

endef

$(eval $(call FOO))

There are other alternatives but most depend on the real contents of FOO which you haven't give us. For example, if you really don't use any arguments you don't need call at all. You can also look at the value function.

Upvotes: 1

Related Questions