user3811839
user3811839

Reputation: 141

L1 Buffer handling

The L1 instruction cache contains..... instructions. For what type of instructions would the CPU fetch an instruction from the icache and then need to look-up a virtual address using the L1 instruction Translation Lookaside Buffer (iTLB)? I can see why an instruction would be fetched and then the L1 data TLB is used to look-up a virtual address, but I can't see why the iTLB would be used? What type of x86 instruction would cause this?

Upvotes: 1

Views: 177

Answers (1)

Leeor
Leeor

Reputation: 19706

You swapped the order here.

If the L1 instruction cache is physically tagged (as in the vast majority of CPUs), then you first access the iTLB to convert your instruction pointer / program counter from a virtual address into a physical one, and only then access the L1 with that.

Therefor, since in x86 all the instructions are accessed through the virtual address in the instruction pointer (LIP, or RIP in 64bit mode), except perhaps some wild corner cases of real-mode or uncacheable code, all code fetches would have to go though this process and start with the iTLB before accessing the instructions cache (or any further cache / memory level in case of a miss).

If the cache is also virtually indexed (VIPT, which is also quite common), then you may access them in parallel and read the entire set while you also access the iTLB for the translation. In some cases it may even lead to the L1 cache being accessed earlier (if the iTLB is stressed by other requests, or you miss and have to do a page walk), but you'll still need the translation eventually to identify the correct line through its physical tag, before you can actually start using that instruction by sending it down the pipe.

Note that in some CPUs, you may have other forms of code caching (for e.g. Intels' uop cache), which may present an alternative path. I don't think the actual details are available, but there may be some forms of "relaxed" TLB checks for when you already know what the code is, and only need to inspect the TLB attributes to make sure nothing bad happened (like some other thread changing the pagemap under your feet).

Upvotes: 3

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