CODEWITHSUNDEEP
makefile
dnsmkl
dnsmkl

Reputation: 792

How such makefile works? (is it normal?)

I encountered such pattern in makefile

CXXOBJ = f1.o f2.o f3.o

$(CXXOBJ): %.o: %.cpp
    g++  -c $<  -o $@

f1.o: f1.cpp  f1.hpp  f2.hpp
f2.o: f2.cpp  f2.hpp  f3.hpp  macros.h
f3.o: f3.cpp  f3.hpp



It works (at least with GNU make 4.0).
It uses generic recipe from 4th line,
but in addition uses dependencies defined at the bottom.

Questions

  1. Is it standard make behavior? (or is it specific to GNU-make?)
  2. Is it standard way to write make file? (i.e. are people usualy doing it this way or is it something 'exotic'?)
  3. How exactly does it work?
    How does make combine 2 distinct rules for same file? (just append dependency list or something more?)
    (I was browsing through GNU-make manual, but could not find relevant part)

Upvotes: 2

Views: 41

Answers (2)

keltar
keltar

Reputation: 18399

This is called static pattern rules (https://www.gnu.org/software/make/manual/html_node/Static-Usage.html). It is specific to GNU make. It might be useful when different targets require different recipes to build, but match the same pattern.

As for third question, there are no distinct rules for the same file. Everything is quite well defined, each target have corresponding .cpp file.

Upvotes: 4

perreal
perreal

Reputation: 97978

GNU Make manual:

One file can be the target of several rules. All the dependencies mentioned in all the rules are merged into one list of dependencies for the target....

There can only be one set of commands to be executed for a file. If more than one rule gives commands for the same file, make uses the last set given and prints an error message...

Upvotes: 3

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