CODEWITHSUNDEEP
cmakefile
Aashish Sharma
Aashish Sharma

Reputation: 75

Make error when trying to create *.o

I'm at my wits end here because of this extremely stupid error I'm getting from my makefile. I finally gave up stripped the makefile down to just two lines:

%.o:    %.c
        gcc -c -o $@ $< -I../inc

Command: make . The output:

make: *** No targets.  Stop.

The spaces at the beginning are real tabs instead of spaces. The c files are in the same directory. If instead of %.o I give, say, file1.o and file1.c instead of %.c, all is well (file1.o gets created). I see plenty of examples on the 'net that use the % operator, though. If I include a clean: target, it is promptly found, like so:

%.o:    %.c
        gcc -c -o $@ $< -I../inc
clean:
        echo "this is clean!"

Command: make . The output:

echo "this is clean!"
this is clean!

Please help me out here as I'm totally clueless about what's wrong with my targets. In the second sample (the one with clean target), I guess the clean target is found and acted upon as the first one is 'invalid' somehow.

Upvotes: 1

Views: 324

Answers (4)

Saurabh Meshram
Saurabh Meshram

Reputation: 8436

I see your intention to make only .o files (can be needed for creation of libraries).
You can modify your Makefile to build only .o files or build only executable by using the same Makefile

For the below directory structure (using tree command) 

# tree .
.
|-- include
|   `-- head.h
|-- Makefile
|-- obj
`-- src
    `-- main.c

Makefile 

# GNU Makefile #

# Some Variables #
CC := gcc
RM := rm
MV := mv

# Phony Targets #
.PHONY: clean
.PHONY: move

# Path for Source, Object and Include #
SRC_PATH := ./src/
OBJ_PATH := ./obj/
INCLUDE_PATH := ./include/

# Source and Object File Names #
SRC := $(SRC_PATH)main.c
OBJ := $(SRC:c=o)               # Substitutes all SRC but with .c as .o (main.c becomes main.o) #

# Executable Name #
TARGET := exe

# Building Binary - use 'make' #
binary:         $(TARGET) move

$(TARGET):      $(OBJ)
                $(CC) -o $(TARGET) $^

# Building only Object Files - use 'make object_only' #
object_only :   $(OBJ) move

$(OBJ):         $(SRC)
                $(CC) -c -o $@ $< -I $(INCLUDE_PATH)

# This rule is for moving .o files to ./obj directory (More Organised) #
move:           
                $(MV) $(SRC_PATH)*.o  $(OBJ_PATH)

# For Cleaning - use 'make clean' #
clean:  
        echo "Cleaning Up!"
        $(RM) -rfv $(TARGET) $(OBJ_PATH)*.o $(SRC_PATH)*.o      # Delete .o and executable #

Execution:

To build only object files use 

$ make object_only

To build object files and executable, use 

$ make

Upvotes: 0

lihudi
lihudi

Reputation: 865

Looks like you forgot to write a target. You have just written rules of how to compile, but not what to do with those objects. I mean, I miss something like:

my_executable_file: *.o
    gcc -o my_executable_file *.o

EDIT:

What is set before is true, you need a target. But as you want only to compile, your target should be something like:

OBJECTS = file.o #and whatever objects you need, as a list separated by commas

And then your target:

my_objects: $(OBJECTS)

So putting it all together:

OBJECTS = file.o #and whatever objects you need, as a list separated by commas
my_objects: $(OBJECTS)
%.o:    %.c
    gcc -c -o $@ $< -I../inc

Upvotes: 1

Yotam
Yotam

Reputation: 898

When an explicit target is not given to make, then the first (non-pattern?) target in the Makefile is used. In the case above, it is the clean target.

Upvotes: 0

Santosh A
Santosh A

Reputation: 5361

Below is the Makefile that will enable to any number of targets to compile

OBJ :=  file.o

all: $(OBJ)

%.o: %.c
    gcc -c -o $@ $< -I../inc
clean:
    echo "this is clean!"

Here, OBJ will be the list of the files that you want to compile , like here it is file.c

Add the file name you want to compile to OBJ, when make is called it will build the target all first which depends on the OBJ.

To build OBJ the gcc command is used.

Upvotes: 0

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