CODEWITHSUNDEEP
makefile
Will
Will

Reputation: 75673

Target dependencies from variable in Makefile

(GNU Makefile)

I want a target that builds any library with the naming convention lib*.so, and depends upon a list of object files specified in a variable.

E.g. to build libabc.so would depend upon the .o files in the variable abc_OBJS.

I have tried lib%.so: $($(%)_OBJS), but that's not right.

What is the syntax?

Upvotes: 1

Views: 1687

Answers (1)

Didier Trosset
Didier Trosset

Reputation: 37477

I guess you cannot do this. GNU Make manual explicitly states:

Note that expansion using ‘%’ in pattern rules occurs after any variable or function expansions, which take place when the makefile is read.

.SECONDEXPANSION makes it work! (Note it's not SECONDARY, but SECOND)

The following Makefile:

abc_OBJS=a.o b.o c.o
def_OBJS=d.o e.o f.o

%.o:
    touch $@

.SECONDEXPANSION:

lib%.so: $$(%_OBJS)
    @echo $@ $^

Results in what you want!

$ make libabc.so libdef.so
touch a.o
touch b.o
touch c.o
libabc.so a.o b.o c.o
touch d.o
touch e.o
touch f.o
libdef.so d.o e.o f.o
rm a.o b.o c.o e.o d.o f.o

Note that if there's no rule to create the dependencies (%.o: rule) then the pattern rule does not match.

Upvotes: 1

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