CODEWITHSUNDEEP
makefile
alkalinity
alkalinity

Reputation: 2040

Set Makefile variable before target dependency

I'm working on a Makefile for building one or all targets from a list TARGETS (in this example, RPMS for one or many architectures).

If the variable TARGET is given, that particular RPM is built. If the variable TARGET is not set, the rule for each TARGET in TARGETS would be invoked, i.e.:

TARGETS = x86_64 i686
ifdef TARGET
all: $(TARGET)
else
all: $(TARGETS)
endif

<magical part:>
$(TARGETS): TARGET = $@: rpm

rpm:
  rpmbuild --target=$(TARGET) SPECS/foo.spec

I also tried:

TARGETS = x86_64 i686
ifdef TARGET
all: $(TARGET)
else
all: $(TARGETS)
endif

<magical part:>
$(TARGETS): TARGET = $@
$(TARGETS): rpm

rpm:
  rpmbuild --target=$(TARGET) SPECS/foo.spec

Can this be done, or would I be better off calling make anew for each target, e.g.:

TARGETS = x86_64 i686
ifdef TARGET
all: rpm
else
all: $(TARGETS)
endif

$(TARGETS):
  make TARGET=$@

rpm:
  rpmbuild --target=$(TARGET) SPECS/foo.spec

Ideal invocation would be TARGET=x86_64 make equivalent to make x86_64.

Upvotes: 0

Views: 856

Answers (1)

Beta
Beta

Reputation: 99164

I'm not entirely sure why you want to do this, but here's one way to do it:

TARGETS = a b c
ifdef TARGET
all: $(TARGET)
else
all: $(TARGETS)
endif

$(sort $(TARGETS) $(TARGET)):
    @echo $@

The sort function removes duplicates. If your TARGET is one of the elements in TARGETS, Make will complain about a duplication in the target list, unless you remove it.

Upvotes: 1

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