CODEWITHSUNDEEP
syntaxverilog
thetypist
thetypist

Reputation: 333

NAND and NOT operators

I would like to convert the following into NAND and NOT gates only in Verilog HDL.

A & B | C

I tried the following in Verilog:

A &~ B &~ ~C

However, I get a syntax error at token ~ in the ~C.

Upvotes: 0

Views: 525

Answers (1)

Qiu
Qiu

Reputation: 5761

You can do it that way:

~(~(A&B) & ~C)

Upvotes: 2

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