CODEWITHSUNDEEP
macrosmakefile
Ron
Ron

Reputation: 2019

Limiting Make's @echo command

I'm trying to write a Makefile macro that call two macros one after the other. The first macro echos something and the second macro calls gcc. The problem is, make expands both these macros and the result is the gcc command is just echoed and does not run.

Here's an example:

funca = @echo "foo $1"
funcb = gcc --version
funcc = $(call funca,$1) $(call funcb,$1)

all:
    $(call funcc,"bar")

The output I get is foo bar gcc --version, but what I want is foo bar and the actual output of gcc --version (preferably on a new line). Breaking the macro with a newline and a backslash doesn't do any good, and wrapping the gcc command in a $(shell ...) macro doesn't work either.

Any idea on how this should be done?

Upvotes: 0

Views: 99

Answers (1)

MadScientist
MadScientist

Reputation: 100866

I'm not sure why you want to do this, but if you want to run multiple shell commands in the same recipe command line you have to separate them with some kind of shell separator such as ; or &&.

The result of your $(call funcc,"bar") is the string echo "foo "bar"" gcc --version so that's the command that's sent to the shell. If you type that into the shell you'll see it will just print the string foo bar gcc --version, just as you'd expect.

If you want to run multiple commands separate them; for example:

funcc = $(call funca,$1) && $(call funcb,$1)

Upvotes: 1

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