Asbjørn Djupdal
Reputation: 31
Memory mapped I/O on the riscv rocket core
How can I do uncached memory accesses on the rocket? Is there a way to specify which regions of the memory map that should have caches enabled or disabled?
I can not find anything about this in any documentation, but if I have overlooked something I would be happy to receive a link to where this is documented.
Asbjørn
Upvotes: 1
Views: 1011
Answers (1)
Asbjørn Djupdal
Reputation: 31
This was answered on the riscv sw-dev mailing list. It is not possible to do uncached memory access on the rocket core.
https://lists.riscv.org/lists/arc/sw-dev/2014-10/msg00025.html :
Rocket's data cache doesn't support uncached loads and stores. Our test chips perform I/O using control registers via the CSRxx instructions.
Upvotes: 2
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