vhdl 4 bit vedic multiplier

Question

entity fourbitmult is
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
       p : out  STD_LOGIC_VECTOR (7 downto 0));
 end fourbitmult;

 architecture Behavioral of fourbitmult is
 component twobitmult

 port(a,b:in std_logic_vector(1 downto 0);
 p:out std_logic_vector (3 downto 0));
 end component;
component rca
port(a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
carry:out std_logic;
cin:in std_logic='0'
);
 end component;
component halfadder
port(a,b:in std_logic;
s,c:out std_logic);
end component;
signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22: std_logic;
begin
m1:twobitmult port map(a(0),a(1),b(0),b(1),p(0),p(1),c1,c2);
m2:twobitmult port map(a(2),a(3),b(0),b(1),c15,c16,c17,c18);
m3:twobitmult port map(a(0),a(1),b(2),b(3),c19,c20,c21,c22);
m4:twobitmult port map(a(2),a(3),b(2),b(3),c7,c8,c9,c10);
r1:rca port map(c15,c16,c17,c18,c19,c20,c21,c22,c3,c4,c5,c6,c12);
r2:rca port map(c1,c2,c7,c8,c3,c4,c5,c6,p(2),p(3),p(4),p(5),c11);
c13<=c11 or c12;
h1:halfadder port map(c13,c9,p(6),c14);
h2:halfadder port map(c14,c10,p(7));
end Behavioral;

I wrote a VHDL code for the 4 bit vedic multiplier. I am getting an error as:

Line 45. parse error, unexpected EQ, expecting SEMICOLON or CLOSEPAR"..

The syntax is perfectly right, I don't understand why it's an error. What could be wrong?

Answer 1

The syntax is perfectly right

Not quite.

cin:in std_logic='0'

Should be

cin: in std_logic := '0'
------------------^

You're also missing the context clause at the beginning:

library ieee;
use ieee.std_logic_1164.all;

You've deleted that and some header comments apparently, without indicating which line was line 45 (and it's the line excerpted above). Your example isn't quite a Minimal, Complete, and Verifiable example.

Syntax errors tend to show up easily when you use white space and indentation consistently and well.

Willing to make a claim about the semantics?

Addendum for " More actuals found than formals in port map"

As you've discovered you also have semantic errors as well as the above syntax error. While you didn't update your question, those errors can be explained here too.

The " More actuals found than formals in port map" for original lines 54 - 59 are because you don't have the same number of ports in the port map associations as are declared in the component declarations for twobitmult and rca instances.

You can cure these by using named association which allows you to use a formal's array port elements associated with an array base element type actual. (Allowing more association list entries than the number of ports).

Note that you appear to have an error with the rca component declaration, there are more port map associations shown than are possible by expanding array types.

It appears carry is intended to be an array type (and the following has been annotated to reflect that).

Also note that your array types in your components are declared with port element indexes in a descending order and you associate them with ascending order elements of entity fourbitmult array type ports.

Should you be able to use slices of the actuals with the same range direction as they are declared the association list entry could be simplified as a => a(1 downto 0), for example. The same holds true for other places you can connect slice actuals.

So making the number of ports match by using formal elements:

library ieee;
use ieee.std_logic_1164.all;

entity fourbitmult is
    port ( 
        a,b:        in   std_logic_vector (3 downto 0);
        p:          out  std_logic_vector (7 downto 0));
 end fourbitmult;

architecture behavioral of fourbitmult is
    component twobitmult
        port (
            a,b:    in  std_logic_vector (1 downto 0);
            p:      out std_logic_vector (3 downto 0)
        );
    end component;
    component rca
        port ( 
            a,b:    in  std_logic_vector (3 downto 0);
            s:      out std_logic_vector (3 downto 0);
            carry:  out std_logic_vector (3 downto 0); -- std_logic;
            cin:    in  std_logic := '0'  -- formerly line 45
    );
    end component;
    component halfadder
        port (
            a,b:    in  std_logic;
            s,c:    out std_logic
        );
    end component;
    signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,
           c13,c14,c15,c16,c17,c18,c19,c20,c21,c22: std_logic;
begin
m1:
    twobitmult 
        port map (
            -- a(0),a(1),b(0),b(1),p(0),p(1),c1,c2
            a(1) => a(0), 
            a(0) => a(1), 
            b(1) => b(0),
            b(0) => b(1),
            p(3) => p(0),
            p(2) => p(1),
            p(1) => c1,
            p(0) => c2
        );
m2:
    twobitmult 
        port map ( 
            -- a(2),a(3),b(0),b(1),c15,c16,c17,c18
            a(1) => a(2),
            a(0) => a(3),
            b(1) => b(0),
            b(0) => b(1),
            p(3) => c15,
            p(2) => c16,
            p(1) => c17,
            p(0) => c18
        );
m3:
    twobitmult 
        port map (
            -- a(0),a(1),b(2),b(3),c19,c20,c21,c22
            a(1) => a(0),
            a(0) => a(1),
            b(1) => b(2),
            b(0) => b(3),
            p(3) => c19,
            p(2) => c20,
            p(1) => c21,
            p(0) => c22
        );
m4:
    twobitmult 
        port map (
            -- a(2),a(3),b(2),b(3),c7,c8,c9,c10
            a(1) => a(2),
            a(0) => a(3),
            b(1) => b(2),
            b(0) => b(3),
            p(3) => c7,
            p(2) => c8,
            p(1) => c9,
            p(0) => c10
        );
r1:
    rca 
        port map (
             --c15,c16,c17,c18,c19,c20,c21,c22,c3,c4,c5,c6,c12
             a(3) => c15,
             a(2) => c16,
             a(1) => c17,
             a(0) => c18,
             b(3) => c19,
             b(2) => c20,
             b(1) => c21,
             b(0) => c22,
             carry(3) => c3,
             carry(2) => c4,
             carry(1) => c5,
             carry(0) => c6,
             cin  => c12
        );
r2:
    rca 
        port map (
            -- c1,c2,c7,c8,c3,c4,c5,c6,p(2),p(3),p(4),p(5),c11
            a(3) => c1,
            a(2) => c2,
            a(1) => c7,
            a(0) => c8,
            b(3) => c3,
            b(2) => c4,
            b(1) => c5,
            b(0) => c6,
            carry(3) => p(2),
            carry(2) => p(3),
            carry(1) => p(4),
            carry(0) => p(5),
            cin  => c11
        );

        c13 <= c11 or c12;

h1:
    halfadder 
        port map ( 
            c13,c9,p(6),c14
        );
h2:
    halfadder 
        port map ( 
            c14,c10,p(7)
        );
end behavioral;

This analyzes, but without the entity/architecture pairs for the declared components can't be elaborated, nor the functionality verified.