CODEWITHSUNDEEP
vhdl
zach thomas
zach thomas

Reputation: 1

VHDL for loop in test bench to run truth table

How would I do this in a VHDL test bench to run through a truth table for a multiplexer. Am I on the right track?

sel <= "00" after 100 ns, "01" after 200 ns, "10" after 300 ns, "11" after 400;

process (sel)
    variable p :STD_LOGIC_VECTOR(3 downto 0); 
begin
    p := "0000"
    for j in "0001" to "1111" loop
        if j /= "1111" then p:= p + 1;
        wait for 5 ns; 
    end loop ;
end process;

x <= p;

Upvotes: 0

Views: 5581

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

Keep generation of sel (select) and p (data) together, since it is easier to generate with the right timing if these are not decoupled in different assigns or processes. The loops may be created based on natural ranges. The process can then be:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
process is
begin
  for sel_loop in 0 to 2 ** sel'length - 1 loop  -- 0 to 3 for sel'length = 2
    for p_loop in 0 to 2 ** p'length - 1 loop  -- 0 to 15 for p'length = 4
      sel <= std_logic_vector(to_unsigned(sel_loop, sel'length));
      p   <= std_logic_vector(to_unsigned(p_loop, p'length));
      wait for 5 ns;
    end loop;
  end loop;
  wait;
end process;

Waveform is below. enter image description here

Upvotes: 4

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