CODEWITHSUNDEEP
cmakefile
this is213421
this is213421

Reputation: 23

makefile - how to exclude file extension suffix from a variable

the next makefile receive the file to compile from its command line arg -ARGS. For example

make ARGS="out.c"

I would like to replace the name of the created executable "run" with the variable ARGS excluding the suffix

in this example : run="out"

all: Task1
Task1: outputs/output.o
	gcc -g -m32 -Wall -o run outputs/output.o 

outputs/output.o: outputs/${ARGS}
	gcc -m32 -g -w -Wall -ansi -c -o outputs/output.o outputs/${ARGS} 


.PHONY: clean
run: clean Task1
clean:
	rm -f outputs\output.o Task1

Upvotes: 2

Views: 3163

Answers (2)

Beta
Beta

Reputation: 99172

The crude way to do what you ask is simply:

EXEC := $(basename $(ARGS))
all: Task1
Task1: outputs/output.o
    gcc -g -m32 -Wall -o $(EXEC) outputs/output.o

A better way is:

EXEC := $(basename $(ARGS))
all: $(EXEC)
$(EXEC): outputs/output.o
    gcc -g -m32 -Wall -o $(EXEC) outputs/output.o

Better still:

EXEC := $(basename $(ARGS))
all: $(EXEC)
$(EXEC): outputs/output.o
    gcc -g -m32 -Wall -o $@ $^

Upvotes: 3

Basile Starynkevitch
Basile Starynkevitch

Reputation: 1

If using GNU make you need the basename function, perhaps as $(basename $(AUX)). Maybe variables like $(*F) might be useful too (please read the documentation). However, your Makefile is probably wrong.

I can't suggest an improvement, because what you want to do and to happen is unclear.

BTW, use remake (as remake -x) or at least make --trace (with a recent enough GNU make 4.x) to understand what make is doing and why.

Also, you'll find several examples of Makefile-s: here & there etc... Don't forget that make has a many builtin rules, you'll get them by running make -p

You won't lose your time by reading the documentation of GNU make, and some tutorials, and some examples of Makefile-s.

Upvotes: 1

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