Reputation: 44807
I have a make project with two real targets, a testsuite and the project's executable.
To build these I want rules something like:
testsuite: *.c (except executable.c) *.h
clang ... *.c (except executable.c) -o testsuite
executable: *.c (except testsuite.c) *.h
clang ... *.c (except testsuite.c) -o executable
What's the correct syntax for this, if it's possible?
Upvotes: 3
Views: 2475
Reputation: 81012
Something like this should do what you want.
# Explicitly list the sources specific to each target.
EXECUTABLE_SOURCES := executable.c
TESTSUITE_SOURCES := testsuite.c
# Filter out all specific sources from the common wildcard-ed sources.
COMMON_SOURCES := $(filter-out $(TESTSUITE_SOURCES) $(EXECUTABLE_SOURCES),$(wildcard *.c))
testsuite: $(TESTSUITE_SOURCES) $(COMMON_SOURCES)
clang ....
executable: $(EXECUTABLE_SOURCES) $(COMMON_SOURCES)
clang ....
Upvotes: 6
Reputation: 310
caveat: I did not test
You could use something like testsuite: $(filter-out executable.c,$(wildcard *.c))
. I think wildcard
function is needed, as you don't want to operate on string "*.c", but its expansion. Prerequisites are expanded automatically, but function arguments are not. From info make
:
Wildcard expansion is performed by 'make' automatically in targets and in prerequisites. In recipes, the shell is responsible for wildcard expansion. In other contexts, wildcard expansion happens only if you request it explicitly with the 'wildcard' function.
Upvotes: 1