CODEWITHSUNDEEP
verilog
Emman
Emman

Reputation: 1234

How range overflow affects the simulation and synthesis?

module dut ( a,b_out,array,c);
input [2:0] a;
input [3:0] array;
input       c;
output reg  b_out;
always@( a or c or array) begin
  if(c)
    b_out = 1'b0;
  else
  b_out = array[a]; 
  end
endmodule

There is a possible range overflow in the above RTL, how it exactly affects the simulation and synthesis?

Upvotes: 1

Views: 567

Answers (1)

CliffordVienna
CliffordVienna

Reputation: 8235

When a > 3 and !c then b_out will be undef in simulation because an out-of bounds access to a vector returns undef (i.e. 1'bx). See 5.2.1 in IEEE Std 1364-2005:

A part-select of any type that addresses a range of bits that are completely out of the address bounds of the net, reg, integer, time variable, or parameter or a part-select that is x or z shall yield the value x when read and shall have no effect on the data stored when written. Part-selects that are partially out of range shall, when read, return x for the bits that are out of range and shall, when written, only affect the bits that are in range.

In synthesis this don't care will be transformed into whatever the synthesis tool deems the most efficient. Very likely that means that only the bottom two bits of a are used in array[a], i.e. it is identical to array[a[1:0]]. But there is no guarantee for that whatsoever and it would be equally correct to create a circuit that for example always returns 1 or 0 when a[2] is high.

Upvotes: 3

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