CODEWITHSUNDEEP
verilogsystem-verilog
dpaul
dpaul

Reputation: 31

How to instiantiate a SystemVerilog module in a top level module

I want to use the SysWip AXI4Lite Slave verification IP (in SystemVerilog) in my top-level test-bench with my traditional Verilog AXI4Lite master.

Being completely new to SystemVerilog, I have problems to port-map in the toplevel testbench.

What I have: From the SysWip I have downloaded axi4lite_s_if.sv which is an interface and the axi4lite_s.sv which is a package (http://syswip.com/axi4-lite-verification-ip). From my legacy code I have a dut_top.v and dut_top_tb.sv (I have renamed it to .sv in order to support some SV constructs - import, creating the slave class object, etc). The Verilog AXI4Lite master module is instiantiated in the dut_top.v

Target: I want to connect the ports of the legacy Verilog AXI4Lite Master to that of the SysWip VIP slave. I am getting a Syntax error message where the ports are being mapped in the dut_top_tb.sv.

So can anyone point me the proper syntax for doing the portmap for the above case?

Upvotes: 1

Views: 3443

Answers (1)

dave_59
dave_59

Reputation: 42788

Your question is confusing because you are mixing module and interface which are similar yet different constructs.

SystemVerilog interface instances can be connected to SystemVerilog modules through interface ports. If you have a legacy Verilog module without interface ports, you can still connect an SV interface instacne to a Verilog module by using a hierarchical reference. For example

interface intf;
 wire w;
endinterface
module verilog_dut(input wire w);
  initial $display(w);
endmodule
module SV_dut(intf p);
  initial $display(p.w);
endmodule
module top;
  intf i1();
  verilog_dut i2(.w(i1.w));
  SV_dut i3(.p(i1));
endmodule

Upvotes: 1

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