CODEWITHSUNDEEP
vhdl
Forzacule
Forzacule

Reputation: 19

Generated random number VHDL

I need to generate random binary numbers of 13 bits in a test_bench . Then, when the start signal is set to 1 , generates a random num_bin . Why in my code it is not generated ? I mean, it generates 0000000000000 , when should generate a 13-bit number either . What can be wrong? Thank You

Note : num_bin input is a number that I have to give it in another process .

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 reset <= '1', '0' after 75 ns;
 inicio <='0', '1' after 100 ns;

 process
 variable seed1 :integer ;
 variable seed2 :integer ;
 variable re1 : integer;
 variable re2 : real ;
 begin  

    if inicio = '1' then
    uniform (seed1,seed2,re2);
    re1 := integer (re2 * real(2**13 -1));  
   num_bin <= std_logic_vector ( to_unsigned (re1,13));
    end if;
 wait;
 end process;

Upvotes: 1

Views: 16612

Answers (2)

user1155120
user1155120

Reputation:

Removing the condition in the process and changing seed1, seed2 to positives and letting the process generate more than one num_bin value:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;

entity uni is
end entity;

architecture foo of uni is
    signal num_bin: std_logic_vector (12 downto 0);
begin
    
NOLABEL:
    process
    variable seed1 :positive ;
    variable seed2 :positive ;
    variable re1 : integer;
    variable re2 : real ;
    begin  

       -- if inicio = '1' then
       uniform (seed1,seed2,re2);
       re1 := integer (re2 * real(2**13 -1));  
      num_bin <= std_logic_vector ( to_unsigned (re1,13));
       -- end if;
    wait for 10 ns;
    if Now > 50 ns then
        wait;
    end if;
    end process;
    
MONITOR:
    process (num_bin)
    begin
        report "uniform = " & to_string(num_bin) severity NOTE;
    end process;
end architecture;

And we get:

$GHDL -r uni
uni.vhdl:44:9:@0ms:(report note): uniform = uuuuuuuuuuuuu
uni.vhdl:44:9:@0ms:(report note): uniform = 1111111111111
uni.vhdl:44:9:@10ns:(report note): uniform = 1111100101110
uni.vhdl:44:9:@20ns:(report note): uniform = 1010010111000
uni.vhdl:44:9:@30ns:(report note): uniform = 0101010101000
uni.vhdl:44:9:@40ns:(report note): uniform = 0000100101111
uni.vhdl:44:9:@50ns:(report note): uniform = 0010100101101

The first non-initial value of all '1's is likely a result of the initial values for seed1 and seed2 for type positive.

If your not getting anything but all '0's, are you initializing num_bin to '0's?

Add your conditional evaluation back in and initialize num_bin:

architecture fum of uni is
    signal num_bin: std_logic_vector (12 downto 0) := (others => '0');
    signal inicio: std_logic;
begin
    inicio <='0', '1' after 100 ns;
NOLABEL:
    process
    variable seed1 :positive ;
    variable seed2 :positive ;
    variable re1 : integer;
    variable re2 : real ;
    begin  
        if inicio = '1' then
            uniform (seed1,seed2,re2);
            re1 := integer (re2 * real(2**13 -1));  
            num_bin <= std_logic_vector ( to_unsigned (re1,13));
        end if;
        wait;
    end process;
    
MONITOR:
    process (num_bin)
    begin
        report "uniform = " & to_string(num_bin) severity NOTE;
    end process;
end architecture;

And we get:

$GHDL -r uni
uni.vhdl:71:9:@0ms:(report note): uniform = 0000000000000

And if we don't initialize num_bin we get all 'U's.

The reason why is the wait statement in your unlabelled process. Your process will execute exactly once, encounter the wait and never execute again. That execution occurs during initialization.

IEEE Std 1076-2008 14.7.5 Model execution, 14.7.5.1 General

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. ...

I'll switch to 1076-1993 12.6.4 The Simulation cycle because it's not encumbered by things not of interest in this context. It's a subset of what occurs in the execution of a -2008 model.

At the beginning of initialization, the current time, Tc, is assumed to be 0 ns.

The initialization phase consists of the following steps:

-- The driving value and the effective value of each explicitly declared signal are computed, and the current value of the signal is set to the effective value. This value is assumed to have been the value of the signal for an infinite length of time prior to the start of simulation.

All objects in VHDL have a value. Without supplying a default value in the declaration of inicio the default value is it's 'LEFT value, which in this case is 'U'.

Without a default value for inicio that passes muster for the condition in the if statement, we don't invoke execution of the sequence of statements enclosed by the if statement. The following wait statement insures the process won't execute again. We never generated a random number value for num_bin.

And removing the if statement conditional on inicio isn't sufficient. We can see that without generating a random or at least non 1 value for either or both of seed1 and seed2 will get a first value of all '1's on num_bin. (And without random seed first values the sequence of values produced by UNIFORM calls are repeatable).

Upvotes: 1

Philippe
Philippe

Reputation: 3730

If you want to generate random numbers in VHDL, look at the open source OSVVM library. http://www.osvvm.org

Upvotes: 1

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