CODEWITHSUNDEEP
cachingcpu-architecture
secondubly
secondubly

Reputation: 1032

Calculating Effective CPI when using write-through/write-back architecture

So I'm trying to understand a homework problem given by an instructor and I'm honestly lost - I understand the concept of write-through/write-back, etc. but I can't figure out the actual calculations needed for the effective CPI, could anyone give me a hand? (The problem follows:

The following table provides the statistics of a cache for a particular program. It is known that the base CPI (without cache misses) is 1. It is also known that the memory bus bandwidth (the bandwidth to transfer data between cache and memory) is 4 bytes per cycle, and it takes one cycle to send the address before data transfer. The memory spends 10 cycles to store data from bus or fetch data to bus. The clock rate used by memory and the bus is a quarter of the CPU clock rate.

Data reads per 1000 instructions: 100
Data writes per 1000 instructions: 150
Instruction cache miss rate: 0.4%
Data cache miss rate: 3%
Block size in bytes: 32

Upvotes: 1

Views: 1894

Answers (1)

Craig S. Anderson
Craig S. Anderson

Reputation: 7374

The effective CPI is the base CPU plus the CPI contribution from cache misses.

The cache miss CPI is the sum of the of instruction cache CPI and data cache CPI.

The cache miss cost is the cost of reading or writing to memory, so we will need that.

The cost in bus cycles is 1 (for the address) plus 10 (memory busy time) + 8 (32 byte blocks size divided by 4 bytes/cycle) = 19 cycles. Multiply this by 4 to get CPU cycles. Total is 76 CPU cycles.

So the cost for I cache misses is .004 * 76 = .304 cycles.

The cost for D caches misses is (.10 + .15) * .03 * 76 = .57 cycles

So the effective CPI is 1 + .304 + .57 = 1.874 cycles.

Upvotes: 1

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