CODEWITHSUNDEEP
fpga
Sorena
Sorena

Reputation: 17

How long takes a multiplier function on FPGA? and is it possible to calculate this time?

I have implemented a hardware architecture on FPGA and i use some multiplier function on this architecture ,

I'd like to know is there any way or method on ISE software or hardware (by using chip scope) to calculate the maximum delay time of each section/step?

for example i want to know if i increase the input clock pulse, which sections won't work correctly?

Upvotes: 0

Views: 373

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

Look at the timing report for the design, which can give you delay information about various elements in a requested path.

Based on this you can also get minimum slack information, which then tells you how much you may increase the clock, and you can then change the clock frequency and rerun synthesis to check that it holds timing with the new clock frequency.

Using specific measurement, from for example chip scope, only gives information about that specific chip, on that specific power supply, with that specific data, etc., where the timing engine (Static Timing Analysis (STA)) given you a worst case analysis for design and vendor parameters.

Upvotes: 3

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