CODEWITHSUNDEEP
verilogsynthesis
user2014
user2014

Reputation: 21

Assignment under multiple single edges is not supported for synthesis

I have written this code:

module Key_Schedule(
    subkey_tupple1,
    subkey_tupple2,
    generate_key_final_step,
    rst,clk
);

    reg [0:31] a1,b1,a2,b2;
    input [0:31] subkey_tupple1;
    input [0:31] subkey_tupple2;
    //input [31:0] subkey_A_swap;
    //input [31:0] subkey_B_swap;
    input clk,rst;
    output reg [0:63] generate_key_final_step;
    reg [0:63] temp;
    reg [0:63] round_sub_key_left;

    always @(posedge clk or negedge rst)
    begin
        if (!rst)
        begin
            temp<={64{1'b0}};
            round_sub_key_left<={64{1'b0}};
        end
        else
            temp<={subkey_tupple1[0:31],subkey_tupple2[0:31]};

//The error is below... line 49
        round_sub_key_left<={temp[8:15],temp[16:23],temp[24:31],temp[0:7],temp[40:47],temp[48:55],temp[56:63],temp[32:39]};
        a1={temp[8:15],temp[16:23],temp[24:31],temp[0:7]};
        b1={temp[40:47],temp[48:55],temp[56:63],temp[32:39]};
        a2=b1;
        b2=a1^b1;
        generate_key_final_step={a2,b2};
    end
endmodule

When I click Synthesize -XST I get this error:

ERROR:HDLCompiler:1128 - "D:\Embedded_Project\Key_Schedule.v" Line 49: Assignment under multiple single edges is not supported for synthesis

Upvotes: 1

Views: 5886

Answers (2)

Alexey Birukov
Alexey Birukov

Reputation: 1680

else at line 47 affects only one line, and it is not right. Under reset condition round_sub_key_left has two conflicting drivers. Place code after else in begin-end parentheses.

Upvotes: 1

Greg
Greg

Reputation: 19112

There is a missing begin-end around the else condition. Therefore the assignment to temp is the only assignment in the else condition. When in active reset round_sub_key_left is still derived from temp. There error is likey do to the fact that during asynchronous reset round_sub_key_left is not being assigned to a constant.

Also, at toolic mentioned: It is generally a bad practice to put your combinational logic and synchronous logic in the same always block (ie mix blocking and non-blocking assignments). The best practice is to put combinational logic in an always @* block with blocking assignments (=). Synchronous logic (ie flip-flop) should go in an always @(posedge clk /*+ async-set/set*/) and only use non-blocking assignment (<=).

always @(posedge clk or negedge rst) begin
  if (!rst) begin
    temp<={64{1'b0}};
    round_sub_key_left<={64{1'b0}};
  end
  else begin
    temp <= {subkey_tupple1[0:31],subkey_tupple2[0:31]};
    round_sub_key_left <= temp[8:31],temp[0:7],temp[40:63],temp[32:39]};
  end
end
always @* begin : output_comb_logic
    a1={temp[8:15],temp[16:23],temp[24:31],temp[0:7]};
    b1={temp[40:47],temp[48:55],temp[56:63],temp[32:39]};
    a2=b1;
    b2=a1^b1;
    generate_key_final_step={a2,b2};
end

Upvotes: 2

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