Canonical term for "simultaneous data-latching"

Question

I have a module (in my case on an FPGA) where several input values (registers) are updated sequentially (if at all), but are all copied in parallel in a single, atomic step to guarantee coherency during the following data processing steps. Is there a common term for this?

• "Double-Buffering" comes close, but usually refers to two buffers in parallel that are swapped, while I'm actually copying them "forward".
• "Simultaneous data-latching" is what I'm using at the moment, but it sounds unfamiliar...

Illustration

               store_1             store_all             do_stuff
                  |                    |                     |                               
                +-+-+                +-+-+                 +-+-+                                       
   value_1 -->  |Reg| --- int_1 -->  |Reg| --> input_1 --> | M |                                                          
                +---+                +---+                 | o |                                    
                                       |                   | d |
               store_2                 |                   | u | --> outputs                             
                  |                    |                   | l |                                
                +-+-+                +-+-+                 | e |                                    
   value_2 -->  |Reg| --- int_2 -->  |Reg| --> input_2 --> |   |                                                           
                +---+                +---+                 +---+                                   

                 __  ____________________
    value_1      __><____________________       


    store_1      ______|_________________                                                                                       

                 _______  _______________
    input_1      _______><_______________


                 __________  ____________
    value_2      __________><____________                                                                                     


    store_2      ______________|_________                                               

                 _______________  _______
    input_2      _______________><_______



    store_all    ____________________|___

                 _____________________  _
    out_1        _____________________><_

                 _____________________  _
    out_2        _____________________><_


    do_stuff     _______________________|

Here store_1, store_2 and store_all are write-enable signals for their registers, are synchronously clocked with the same clock.

Answer 1

Looks like basic shift-registers to me.

This type of arrangement might be called retiming registers if there presence is purely to help ease the routing pressure to 'Module'. Or perhaps pipelining registers if they are inserted to maintain some specific alignment between 'value_1/value_2' and 'outputs', say if the latency through Module changed at some point.

If control signals store_1 / store_2 /store_all are infact clocks, they may be called synchronisation stages, although the design has problems in this case.

Your question mixes words that are tangentially related to digital logic timing, without being specific.