CODEWITHSUNDEEP
riscvchiselrocket
Caylen Lee
Caylen Lee

Reputation: 75

Showing Chisel signals in VCD

I'm working with a RISC-V Rocket chip. I added some of my own signals and logic and wanted to see the values of existing signals in the Rocket chip that aren't already shown in the VCD waveform. How do I dump these signals in the VCD file?

Upvotes: 2

Views: 660

Answers (1)

Chris
Chris

Reputation: 3987

There are a number of reasons a signal in Chisel will not show up in the vcd waveform.

First, your design isn't using the signal. Something like val test = inst(13) will be pruned and not emitted if nobody reads the test signal. I believe Chisel may have a debug(test) construct to force it to exist, but I'm not sure.

Second, signals may get renamed during elaboration and show up as different signals. Something like val a = b may mean that b doesn't show up in the waveform, but a does.

Third, typically Chisel signals not in the highest scope will not show up. For example, signals defined locally within when() statements.

Four, memories don't show up by default. They are typically too big to be feasibly dumped. If you are truly sure your memories aren't too big, you can pass a flag to Chisel called --vcdMem.

Upvotes: 3

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